The present invention relates to a liquid crystal display device (hereinafter referred to as LCD) and a driver circuit thereof. In particular, the invention relates to an active matrix LCD in which a number of pixels that are arranged two-dimensionally in matrix form are sequentially selected on a pixel-by-pixel basis, and to a vertical driver circuit thereof.
Among driving methods of an active matrix LCD are a 1H inversion driving method and a dot inversion driving method. In the 1H inversion driving method, the polarity of video signals applied to respective pixels is inverted every 1H (H: horizontal period) with respect to a common voltage VCOM. In the dot inversion driving method, the polarities of video signals applied to adjacent pixels (dots) are inverted alternately.
Selection is made between the above two driving methods in accordance with an intended use. The 1H inversion driving method is mainly used in small-size LCDs. By combining the 1H inversion driving method with a common inversion driving method in which a common voltage VCOM that is applied to opposed electrodes of liquid crystal cells of the respective pixels is inverted every 1H, reduction in voltage and power consumption is attained in a source driver (i.e., a horizontal driver circuit) and hence in the active matrix LCD.
The common inversion driving method, which is useful for reduction in voltage and power consumption, is widely used in medium-size LCDs (about 12 inches). In the common inversion driving method, the output voltage of a scan driver (vertical driver circuit) needs to have a negative low-voltage-side potential. The reason will be explained below with reference to FIG. 1 (equivalent circuit of a pixel section) and FIG. 2 (waveforms).
Assume that VCOMc represents the center potential of a common voltage VCOM and Vcom represents its amplitude, and that the common voltage VCOM is inverted every 1H in the following manner:
CVOM=VCOMcxc2x1(1/2)Vcom
In this case, a voltage VA that is held at node A is shifted by
xcex94VA=xc2x1(Cs+CLC)Vcom/(Cs+CLC+Cp)
where Cs is the capacitance value of an auxiliary capacitor 101, CLC is the capacitance value of a liquid crystal cell 102, and Cp is the capacitance value of a parasitic capacitance at node A of a pixel transistor 103.
If the potential VA at node A has become lower than the potential of a scanning line (gate line) 104 and the pixel transistor 103 has been turned on, the holding potential VA at node A is varied and a bright spot or the like possibly occurs. Therefore, so that the pixel transistor 103 is never turned on in a non-selection period, it is necessary that the output voltage of the scan driver have a negative low-voltage-side potential. FIG. 3 shows an example of a conventional scan driver that outputs a negative low-voltage-side potential. Specifically, FIG. 3 shows the configuration of an output stage of a certain row of the scan driver.
In the output stage of this conventional scan driver, assume a case where the low-voltage-side potential of the scan driver is set at xe2x88x924 V. For example, four CMOS inverters 111-114 are connected to each other in cascade. For example, +15 V is commonly applied to the respective stages of the CMOS inverters 111-114 as a positive-side power source voltage vdd. On the other hand, xe2x88x921 V, xe2x88x922 V, xe2x88x923 V, and xe2x88x924 V are applied to the respective stages of the CMOS inverters 111-114 as negative-side power source voltages vss, vss1, vss2, and vss3. That is, negative voltages are applied so as to increase in absolute value step by step in such a range that the transistors of each stage is not turned on completely.
However, in the conventional scan driver having the above configuration, since the negative-side power source voltages for the first to fourth CMOS inverters 111-114 are so set as to decrease in order, the negative-side power source voltage for a certain stage is necessarily lower than that for the preceding stage and hence a through-current (DC current) flows through the second and following CMOS inverters 112-114. This causes a problem of large current consumption. In particular, the through-current and hence the current consumption increase as the absolute values of the negative-side power source voltages increase.
The amplitude of a final output voltage vout is determined by the on-resistance ratio between the PMOS transistor and the NMOS transistor of the fourth-stage CMOS inverter 114. This causes another problem that the high-voltage-side potential of the output voltage vout drops from +15 V by xcex94V. FIG. 4 shows waveforms of the positive-side power source voltage vdd, the negative-side power source voltages vss, vss1, vss2, and vss3, and output voltages va, vb, vc, and vout of the respective CMOS inverters 111-114.
The present invention has been made in view of the above problems in the art, and an object of the invention is therefore to provide an LCD and a corresponding driver circuit that can reduce voltages and power consumption particularly in the case of accommodating common inversion driving.
According to the invention, in an LCD having a pixel section in which a plurality of pixels are arranged two-dimensionally in matrix form and a plurality of scanning lines are arranged for respective rows, and a driver circuit that sequentially outputs scanning pulses to the respective scanning lines, the driver circuit comprises, in an output stage, a level conversion circuit having a current mirror circuit configuration for shifting at least one of a low-voltage-side potential and a high-voltage-side potential of the scanning pulses.
In the LCD or the driver circuit having the above configuration, the level conversion circuit for shifting the potential of an output voltage as a scanning pulse has a current mirror circuit configuration. Since current flows through the level conversion circuit only during a certain duty period of an input pulse, the power consumption in the level conversion circuit is made small.